The Air Force Research Laboratory’s (AFRL) space vehicles directorate is seeking innovative industry solutions to bolster domestic capacity to build high-performance Strategic Radiation Hardened (SRH) and non-volatile memory (NVM) devices for future systems.

“The United States Space Force is seeking to improve the density and performance of SRH NVMs for future space and strategic systems,” per a Jan. 23 business notice by AFRL for the Advanced Next Generation Strategic Radiation hardened Memory (ANGSTRM) program. “This may be accomplished with a combination of radiation hardening techniques (e.g. RHBP [radiation hardened by process]/RHBD [radiation hardened by design]) applied to SOTA [state-of-the-art] CMOS [complementary metal-oxide-semiconductor] and memory technologies, along with advanced packaging techniques to scale density beyond the levels that could be achieved with a single chip.”

Industry white papers, due by Feb. 13, “shall identify the innovative solutions to achieve government threshold and objective requirements for performance and reliability of advanced SRH NVM, while also considering the SWAP [size, weight and power] constraints of the space environment,” AFRL said. “Successful execution of this program will have broad impact and result in a qualified SRH NVM for use across a wide range of DoD space and strategic systems.”

The radiation and thermal protections required for DoD systems have obviated the use of SOTA, commercial semiconductors in such systems.

“Furthermore, many of the DoD systems have requirements to use trusted, on-shore manufacturing of electronics,” AFRL said. “This has become challenging as many of the advanced semiconductor manufacturing capabilities exist within non-U.S. [chip] foundries. Advancing SRH NVM technologies is critical to support the functionality and modernization of strategic missiles, missile defense and military space systems. The current state-of-the-practice (SOTP) SRH NVM technologies are limited in performance and density, so system designers require multiple (sometimes many) devices to meet on-board storage requirements. This approach drives up the size, weight, power and cost of the system storage solutions. In some cases, limited capability of SOTP technologies prevents programs from reaching desired capabilities.”

Matt Hicks, the director of Northrop Grumman‘s [NOC] Advanced Technology Laboratory (ATL), said last year that ATL is involved in 130 DoD and other federal programs to build and test chips that require high power, unique frequencies, or radiation hardening (Defense Daily, Nov. 2, 2022). When state-of-the-art, small nanometer size chips are needed, Northrop Grumman will buy them from commercial companies.

“There are tons of cases that we’re taking system requirements/designs from other companies,” he said. “We’re leveraging the domestic commercial fab capability. We touch the majority of fabs in this country and go use their chips and reserve the capability of ATL for when those companies can’t produce something or their business model doesn’t drive a need to go do something.”

Northrop Grumman performs full chip testing including wafer, die, and transmit/receive modules.

Sen. Mark Kelly (D-Ariz.), the chairman of the Senate Armed Services Committee’s emerging threats and capabilities panel, has said that the CHIPS and Science Act, signed into law by President Biden last Aug. 9, will not only boost U.S. semiconductor manufacturing and packaging, but testing as well (Defense Daily, Sept. 27, 2022).

Yet, while the CHIPS Act may boost U.S. chip testing and domestic microelectronics manufacturing capacity by more than 1 million wafers per month, the ramp up will take time because of the need “to staff federal program offices, to solicit proposals from industry and academia, to mature a sufficient workforce, and to construct new fabrication facilities,” according to Jared Mondschein, a RAND scientist and analyst of the semiconductor supply chain. “In this interim period, the United States will remain dependent on foreign suppliers,” Mondschein wrote in a RAND blog post. “Further, the expansion of domestic manufacturing capacity may never eliminate the inclusion of foreign suppliers in semiconductor supply chains. The complex and globalized nature of these supply chains suggests it could be impossible to substitute all foreign nodes with domestic suppliers.”

Thus, ensuring that the U.S. supply chain is able to prevent the distribution of counterfeit and faulty microelectronics, especially those related to obsolescent semiconductors, by unauthorized foreign entities will remain a challenge. Mondschein said that the importation of counterfeit microelectronics is “particularly concerning,”

The Semiconductor Industry Association said that 75 percent of global chip manufacturing has been in East Asia and that China has been on track to hold the lead by 2030 “due to its government’s massive investments in this sector.”

The landscape may be shifting, however. For example, Intel Corp. [INTC] is investing $20 billion to build two fabs in Arizona, while Taiwan-based Taiwan Semiconductor Manufacturing Company (TSMC) has built a $12 billion chip plant in the state.

Through the Defense Microelectronics Activity’s (DMEA) Trusted Foundry Program, which certifies U.S.-based computer chip suppliers for varying levels of secure access, DoD has had partnerships with IBM [IBM] and GlobalFoundries, Inc. [GFS], which bought IBM’s chip business in 2014, to build semiconductors domestically. In May 2020, Mark Lewis, the Pentagon’s then director of defense research and engineering for modernization, said that the Trusted Foundry model has “failed from a business standpoint,” and must change its approach to take advantage of commercially available technology (Defense Daily, May 19, 2020).